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19-4715; Rev 5; 2/10
KIT ATION EVALU ABLE AVAIL
16-Bit Microcontroller with Infrared Module
General Description
The MAXQ610 is a low-power, 16-bit MAXQ(R) microcontroller designed for low-power applications including universal remote controls, consumer electronics, and white goods. The MAXQ610 combines a powerful 16-bit RISC microcontroller and integrated peripherals including two USARTs and an SPITM master/slave communications port, along with an IR module with carrier frequency generation and flexible port I/O capable of multiplexed keypad control. The MAXQ610 includes 64KB of flash memory and 2KB of data SRAM. Intellectual property (IP) protection is provided by a secure MMU that supports multiple application privilege levels and protects code against copying and reverse engineering. Privilege levels enable vendors to provide libraries and applications to execute on the MAXQ610, while limiting access to only data and code allowed by their privilege level. For the ultimate in low-power battery-operated performance, the MAXQ610 includes an ultra-low-power stop mode (0.2A, typ). In this mode, the minimum amount of circuitry is powered. Wake-up sources include external interrupts, the power-fail interrupt, and a timer interrupt. The microcontroller runs from a wide 1.70V to 3.6V operating voltage. Dedicated Pointer for Direct Read from Code Space 16-Bit Instruction Word, 16-Bit Data Bus 16 x 16-Bit General-Purpose Working Registers Secure MMU for Application Partitioning and IP Protection Memory Features 64KB Flash: 512 Byte Sectors 20,000 Erase/Write Cycles per Sector Masked ROM Available 2KB Data SRAM Additional Peripherals Power-Fail Warning Power-On Reset/Brownout Reset Automatic IR Carrier Frequency Generation and Modulation Two 16-Bit, Programmable Timers/Counters with Prescaler and Capture/Compare SPI and Two USART Communication Ports Programmable Watchdog Timer 8kHz Nanopower Ring Oscillator Wake-Up Timer Up to 24 (MAXQ610A) or 32 (MAXQ610B) General-Purpose I/Os Low-Power Consumption 0.2A (typ), 2.0A (max) in Stop Mode TA = +25C, Power-Fail Monitor Disabled 3.75mA (typ) at 12MHz in Active Mode
MAXQ610
Applications
Remote Controls Battery-Powered Portable Equipment Consumer Electronics Home Appliances White Goods
Ordering Information Features
PART MAXQ610A-0000+* MAXQ610B-0000+ MAXQ610J-0000+ MAXQ610X-0000+** TEMP RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 32 TQFN-EP 40 TQFN-EP 44 TQFN-EP Bare die
High-Performance, Low-Power 16-Bit RISC Core DC to 12MHz Operation Across Entire Operating Range 1.70V to 3.6V Operating Voltage Range 33 Total Instructions for Simplified Programming Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement
Note: Contact factory for information about masked ROM devices. +Denotes a lead(Pb)-free/RoHS-compliant package. *Future product--contact factory for availability. **Contact factory for availability. EP = Exposed pad. Pin Configurations and Selector Guide appear at end of data sheet.
MAXQ is a registered trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
16-Bit Microcontroller with Infrared Module MAXQ610
TABLE OF CONTENTS
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 SPI Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Stack Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Utility ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 IR Carrier Generation and Modulation Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Carrier Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 IR Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 IR Transmit--Independent External Carrier and Modulator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 IR Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Carrier Burst-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 16-Bit Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 ROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Loading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 In-Application Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 In-Circuit Debug and JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Power-Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Differences for ROM Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Development and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
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16-Bit Microcontroller with Infrared Module MAXQ610
LIST OF FIGURES
Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 3. IR Transmission Waveform (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 4. External IRTXM (Modulator) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 5. IR Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 6. Receive Burst-Count Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 7. SPI Master Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 8. SPI Slave Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 9. On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 10. In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 11. Power-Fail Detection During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 12. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . .24 Figure 13. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
LIST OF TABLES
Table 1. Memory Areas and Associated Maximum Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 3. USART Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 4. Power-Fail Detection States During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . .25
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16-Bit Microcontroller with Infrared Module MAXQ610
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VDD with Respect to GND .......-0.3V to +3.6V Voltage Range on Any Lead with Respect to GND except VDD .....................................-0.3V to (VDD + 0.5V) Operating Temperature Range...............................0C to +70C Storage Temperature Range .............................-65C to +150C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VDD = VRST to 3.6V, TA = 0C to +70C.) (Note 1)
PARAMETER Supply Voltage 1.8V Internal Regulator Power-Fail Warning Voltage for Supply (Notes 2, 3) Power-Fail Reset Voltage (Note 4) Power-On Reset Voltage RAM Data-Retention Voltage Active Current (Note 6) SYMBOL VDD VREG18 VPFW VRST VPOR VDRV IDD_1 I S1 Stop-Mode Current I S2 Current Consumption During Power-Fail Power Consumption During Power-On Reset Stop-Mode Resume Time Power-Fail Monitor Startup Time Power-Fail Warning Detection Time Input Low Voltage for IRTX, IRRX, RESET, and All Port Pins Input High Voltage for IRTX, IRRX, RESET, and All Port Pins Input Hysteresis (Schmitt) Input Low Voltage for HFXIN I PFR I POR tON t PRM_ON t PFW VIL VIH VIHYS VIL_HFXIN GND (Note 5) (Notes 5, 9) 10 GND 0.7 x VDD 300 0.3 x VDD 0.3 x VDD VDD Power-Fail On (Notes 5, 7) (Note 8) Monitors VDD Monitors VDD Monitors VDD (Note 5) Sysclk = 12MHz Power-Fail Off TA = +25C TA = 0C to +70C TA = +25C TA = 0C to +70C CONDITIONS MIN VRST 1.62 1.75 1.64 1.0 1.0 3.75 0.2 0.2 22 27.6 5.1 2.0 12 29.5 42 A nA s s s V V mV V A 1.8 1.8 1.67 TYP MAX 3.6 1.98 1.85 1.70 1.42 UNITS V V V V V V mA
[(3 x I S2) + ((PCI - 3) x (IS1 + INANO))]/PCI 100 375 + 8192tHFXIN 150
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16-Bit Microcontroller with Infrared Module
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = VRST to 3.6V, TA = 0C to +70C.) (Note 1)
PARAMETER Input High Voltage for HFXIN IRRX Input Filter Pulse-Width Reject IRRX Input Filter Pulse-Width Accept Otuput Low Voltage for IRTX SYMBOL VIH_HFXIN t IRRX_R t IRRX_A VDD = 3.6V, I OL = 25mA (Note 5) VDD = 2.35V, I OL = 10mA (Note 5) VDD = 1.85V, I OL = 4.5mA Output Low Voltage for RESET and All Port Pins (Note 10) Output High Voltage for IRTX and All Port Pins Input/Output Pin Capacitance for All Port Pins Input Leakage Current Input Pullup Resistor for RESET, IRTX, IRRX, and All Port Pins EXTERNAL CRYSTAL/RESONATOR Crystal/Resonator Crystal/Resonator Period Crystal/Resonator Warmup Time Oscillator Feedback Resistor EXTERNAL CLOCK INPUT External Clock Frequency External Clock Period External Clock Duty Cycle System Clock Frequency System Clock Period NANOPOWER RING OSCILLATOR Nanopower Ring Oscillator Frequency Nanopower Ring Oscillator Duty Cycle Nanopower Ring Oscillator Current fNANO tNANO INANO TA = +25C TA = +25C, VDD = POR voltage (Note 5) (Note 5) Typical at VDD = 1.64V, TA = +25C (Note 5) 3.0 1.7 40 40 8.0 2.4 60 400 20.0 kHz % nA f XCLK t XCLK t XCLK_DUTY fCK tCK HFXOUT = GND 45 fHFIN f XCLK 1/fCK DC 1/f XCLK 55 12 MHz ns % MHz MHz fHFXIN tHFXIN t XTAL_RDY R OSCF From initial oscillation (Note 5) 0.5 1 1/fHFXIN 8192 x tHFXIN 1.0 1.5 12 MHz ns ms M VOL VDD = 3.6V, I OL = 11mA (Note 5) VDD = 2.35V, I OL = 8mA (Note 5) VDD = 1.85V, I OL = 4.5mA VOH CIO IL RPU I OH = -2mA (Note 5) Internal pullup disabled VDD = 3.0V, VOL = 0.4V (Note 5) VDD = 2.0V, VOL = 0.4V -100 16 17 28 30 VDD 0.5 0.4 0.4 0.4 300 1.0 1.0 1.0 0.5 0.5 0.5 VDD 15 +100 39 41 V pF nA k V V CONDITIONS MIN 0.7 x VDD TYP MAX VDD 50 UNITS V ns ns
MAXQ610
VOL_IRTX
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16-Bit Microcontroller with Infrared Module MAXQ610
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = VRST to 3.6V, TA = 0C to +70C.) (Note 1)
PARAMETER WAKE-UP TIMER Wake-Up Timer Interval FLASH MEMORY System Clock During Flash Programming/Erase Flash Erase Time Flash Programming Time per Word Write/Erase Cycles Data Retention IR Carrier Frequency f IR (Note 5) fCK/2 Hz TA = +25C fFPSYSCLK tME t ERASE t PROG Mass erase Page erase (Note 11) 6 20 20 20 20,000 100 40 40 100 MHz ms s Cycles Years tWAKEUP 1/fNANO 65,535/ fNANO s SYMBOL CONDITIONS MIN TYP MAX UNITS
Specifications to 0C are guaranteed by design and are not production tested. It is not recommended to write to flash memory when the supply voltage drops below the power-fail warning levels as there is uncertainty in the duration of continuous power supply. The user application should check the status of the powerfail warning flag before writing to flash to ensure complete write operations. Note 3: The power-fail warning monitor and the power-fail reset monitor track each other with a minimum delta between the two of 0.11V. Note 4: The power-fail reset and power-on-reset (POR) detectors operate in tandem to ensure that one or both signals are active at all times when VDD < VRST. Doing so ensures the device maintains the reset state until the minimum operating voltage is achieved. Note 5: Guaranteed by design and not production tested. Note 6: Measured on the VDD pin and the part not in reset. All inputs are connected to GND or VDD. Outputs do not source/sink any current. Part is executing code from flash memory. Note 7: The power-check interval (PCI) can be set to always on, 1024, 2048, or 4096 nanopower ring oscillator clock cycles. Note 8: Current consumption during POR when powering up while VDD < VPOR. Note 9: The minimum amount of time that VDD must be below VPFW before a power-fail event is detected. Note 10: The maximum total current, IOH (max) and IOL (max), for all listed outputs combined should not exceed 32mA to satisfy the maximum specified voltage drop. This does not include the IRTX output. Note 11: Programming time does not include overhead associated with utility ROM interface. Note 1: Note 2:
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16-Bit Microcontroller with Infrared Module
SPI ELECTRICAL CHARACTERISTICS
(VDD = VRST to 3.6V, TA = 0C to +70C. AC electrical specifications are guaranteed by design and are not production tested.)
PARAMETER SPI Master Operating Frequency SPI Slave Operating Frequency SPI I/O Rise/Fall Time SCLK Output Pulse-Width High/Low MOSI Output Hold Time After SCLK Sample Edge MOSI Output Valid to Sample Edge MISO Input Valid to SCLK Sample Edge Rise/Fall Setup MISO Input to SCLK Sample Edge Rise/Fall Hold SCLK Inactive to MOSI Inactive SCLK Input Pulse-Width High/Low SSEL Active to First Shift Edge MOSI Input to SCLK Sample Edge Rise/Fall Setup MOSI Input from SCLK Sample Edge Transition Hold MISO Output Valid After SCLK Shift Edge Transition SSEL Inactive SCLK Inactive to SSEL Rising MISO Output Disabled After SSEL Edge Rise SYMBOL 1/tMCK 1/t SCK t SPI_RF tMCH, tMCL tMOH tMOV tMIS tMIH tMLH t SCH, t SCL t SSE t SIS t SIH t SOV t SSH t SD t SLH tCK + t SPI_RF t SPI_RF 2tCK + 2t SPI_RF t SPI_RF t SPI_RF t SPI_RF 2t SPI_RF CL = 15pF, pullup = 560 8.3 tMCK/2 t SPI_RF tMCK/2 t SPI_RF tMCK/2 t SPI_RF 25 0 tMCK/2 t SPI_RF t SCK/2 CONDITIONS MIN TYP MAX fCK/2 fCK/4 23.6 UNITS MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MAXQ610
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16-Bit Microcontroller with Infrared Module MAXQ610
Pin Description
PIN 32 TQFN 15, 29 13, 23, 30 40 TQFN 18, 38 -- 44 TQFN 19, 41 17, 20, 28, 42 NAME FUNCTION POWER PINS VDD GND Supply Voltage Ground. These pins must be directly connected to the ground plane. The 40-pin TQFN package does not have any ground pins and connects to ground through the exposed pad. Regulator Capacitor. This pin must be connected to ground through a 1.0F external ceramic-chip capacitor. The capacitor must be placed as close to this pin as possible. No devices other than the capacitor should be connected to this pin. Exposed Pad. For the 32-pin TQFN package, leave unconnected. For the 40-pin TQFN package, the exposed pad is internally connected to GND. Connect to the ground plane. For the 44-pin TQFN package, the EP has no internal connection to the device. Leave unconnected. Not intended as an electrical connection point. RESET PINS Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this pin is low and begins executing from the reset vector when released. The pin includes pullup current source and should be driven by an open-drain, external source capable of sinking in excess of 4mA. This pin is driven low as an output when an internal reset condition occurs. CLOCK PINS 18 19 21 22 23 24 HFXIN HFXOUT High-Frequency Crystal Input. Connect external crystal or resonator between HFXIN and HFXOUT as the high-frequency system clock. Alternatively, HFXIN is the input for an external, high-frequency clock source when HFXOUT is unconnected. IR FUNCTION PINS IR Transmit Output. IR transmit pin capable of sinking 25mA. This pin defaults to high-impedance input with the weak pullup disabled during all forms of reset. Software must configure this pin after release from reset to remove the highimpedance input condition. IR Receive Input. IR receive pin. This pin defaults to high-impedance input with the weak pullup disabled during all forms of reset. Software must configure this pin after release from reset to remove the high-impedance input condition.
14
17
18
REGOUT
--
--
--
EP
28
37
40
RESET
31
39
43
IRTX
32
40
44
IRRX
8
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16-Bit Microcontroller with Infrared Module
Pin Description (continued)
PIN 32 TQFN 40 TQFN 44 TQFN NAME FUNCTION
MAXQ610
1-8
1, 3, 5-10
1, 3, 5-10
GENERAL-PURPOSE I/O AND SPECIAL FUNCTION PINS General-Purpose, Digital, I/O, Type-C Port. These port pins function as bidirectional I/O pins. All port pins default to high-impedance mode after a reset. Software must configure these pins after release from reset to remove the highimpedance input condition. All alternate functions must be enabled from P0.0- P0.7; 32 TQFN 40 TQFN 44 TQFN PORT SPECIAL FUNCTION IRTXM, 1 1 1 P0.0 IRTXM RX0, TX0, 2 3 3 P0.1 RX0 RX1, TX1, 3 5 5 P0.2 TX0 TBA0/ TBA1, 4 6 6 P0.3 RX1 TBB0/ 5 7 7 P0.4 TX1 TBB1 6 8 8 P0.5 TBA0/TBA1 7 8 9 10 9 10 P0.6 P0.7 TBB0 TBB1
General-Purpose, Digital, I/O, Type-D Port; External Edge-Selectable Interrupt. These port pins function as bidirectional I/O pins or as interrupts. All port pins default to high-impedance mode after a reset. Software must configure these pins after release from reset to remove the high-impedance input condition. All interrupt functions must be enabled from software. 32 TQFN 9-12, 16, 17, 20, 21 11-14, 19, 20, 23, 24 11-14, 21, 22, 25, 26 P1.0- P1.7; INT0- INT7 9 10 11 12 16 17 20 21 40 TQFN 11 12 13 14 19 20 23 24 44 TQFN 11 12 13 14 21 22 25 26 PORT P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 SPECIAL FUNCTION INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7
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9
16-Bit Microcontroller with Infrared Module MAXQ610
Pin Description (continued)
PIN 32 TQFN 40 TQFN 44 TQFN NAME FUNCTION General-Purpose, Digital, I/O, Type-C Port. These port pins function as bidirectional I/O pins. P2.0-P2.3 default to high-impedance mode after a reset. Software must configure these pins after release from reset to remove the highimpedance input condition. All alternate functions must be enabled from software. Enabling the pin's special function disables the general-purpose I/O on the pin. The JTAG pins (P2.4-P2.7) default to their JTAG function with weak pullups enabled after a reset. The JTAG function can be disabled using the TAP bit in the SC register. P2.7 functions as the JTAG test-data output on reset and defaults to an input with a weak pullup. The output function of the test data is only enabled during the TAP's Shift_IR or Shift_DR states. 32 TQFN -- -- -- -- 24 25 26 27 40 TQFN 25 26 29 30 31 32 35 36 44 TQFN 27 29 32 33 34 35 38 39 PORT P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 SPECIAL FUNCTION MOSI MISO SCLK SSEL TCK TDI TMS TDO
24-27
25, 26, 29-32, 35, 36
27, 29, 32-35, 38, 39
P2.0- P2.7; MOSI, MISO, SCLK, SSEL, TCK, TDI, TMS, TDO
General-Purpose, Digital, I/O, Type-D Port; External Edge-Selectable Interrupt. These port pins function as bidirectional I/O pins or as interrupts. All port pins default to high-impedance mode after a reset. Software must configure these pins after release from reset to remove the high-impedance input condition. All interrupt functions must be enabled from software. 32 TQFN -- 2, 4, 15, 16, 27, 28, 33, 34 2, 4, 15, 16, 30, 31, 36, 37 P3.0- P3.7; INT8- INT15 -- -- -- -- -- -- -- -- 23 N.C. 40 TQFN 2 4 15 16 27 28 33 34 44 TQFN 2 4 15 16 30 31 36 37 PORT P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 SPECIAL FUNCTION INT8 INT9 INT10 INT11 INT12 INT13 INT14 INT15
NO CONNECTION PINS No Connection. Reserved for future use. Leave these pins unconnected.
10
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16-Bit Microcontroller with Infrared Module
Block Diagram
peting microcontrollers. An integrated POR circuit with brownout support resets the device to a known condition following a power-up cycle or brownout condition. Additionally, a power-fail warning flag is set and a power-fail interrupt can be generated when the system voltage falls below the power-fail warning voltage, VPFW. The power-fail warning feature allows the application to notify the user that the system supply is low and appropriate action should be taken.
MAXQ610
MAXQ610 REGULATOR VOLTAGE MONITOR GPIO 16-BIT MAXQ RISC CPU 4KB ROM CLOCK WATCHDOG 16-BIT TIMER SECURE MMU 64KB FLASH 2KB SRAM 8kHz NANO RING IR DRIVER IR TIMER SPI USART0 USART1
Microprocessor
The MAXQ610 is based on Maxim's MAXQ core. The MAXQ is a low-power implementation of the new 16-bit MAXQ family of RISC cores. The core supports the Harvard memory architecture with separate 16-bit program and data address buses. A fixed 16-bit instruction word is standard, but data can be arranged in 8 or 16 bits. The MAXQ core in the MAXQ610 family is implemented as a pipelined processor with performance approaching 1MIPS per MHz. The 16-bit data path is implemented around register modules, and each register module contributes specific functions to the core. The accumulator module consists of sixteen 16-bit registers and is tightly coupled with the arithmetic logic unit (ALU). A configurable soft stack supports program flow. Execution of instructions is triggered by data transfer between functional register modules or between a functional register module and memory. Because data movement involves only source and destination modules, circuit-switching activities are limited to active modules only. For power-conscious applications, this approach localizes power dissipation and minimizes switching noise. The modular architecture also provides a maximum of flexibility and reusability that is important for a microprocessor used in embedded applications. The MAXQ instruction set is highly orthogonal. All arithmetical and logical operations can use any register in conjunction with the accumulator. Data movement is supported from any register to any other register. Memory is accessed through specific data-pointer registers with automatic increment/decrement support.
16-BIT TIMER
Detailed Description
The MAXQ610 microcontroller provides integrated, lowcost solutions that simplify the design of IR communications equipment such as universal remote controls. Standard features include the highly optimized, singlecycle, MAXQ 16-bit RISC core, 64KB of flash memory, 2KB data RAM, a soft stack, 16 general-purpose registers, and three data pointers. The MAXQ core offers the industry's best MIPS/mA rating, allowing developers to achieve the same performance as competing microcontrollers at substantially lower clock rates. Combining lower active-mode current with the MAXQ610 stopmode current (0.2A typical) results in increased battery life. Application-specific peripherals include flexible timers for generating IR carrier frequencies and modulation, a high-current IR drive pin capable of sinking up to 25mA current, and output pins capable of sinking up to 5mA ideal for IR applications, generalpurpose I/O pins ideal for keypad matrix input, and a power-fail-detection circuit to notify the application when the supply voltage is nearing the minimum operating voltage of the microcontroller. At the heart of the MAXQ610 is the MAXQ 16-bit RISC core. The MAXQ610 operates from DC to 12MHz and almost all instructions execute in a single clock cycle (83.3ns at 12MHz), enabling nearly 12MIPS true code operation. When active device operation is not required, an ultra-low-power stop mode can be invoked from software resulting in quiescent current consumption of less than 0.2A typical and 2.0A maximum. The combination of high-performance instructions and ultralow stop-mode current increases battery life over com-
Memory
The MAXQ610 incorporates several memory types that include the following: * 64KB program flash * 2KB SRAM data memory * 5.25KB utility ROM * Soft stack
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16-Bit Microcontroller with Infrared Module MAXQ610
Table 1. Memory Areas and Associated Maximum Privilege Levels
AREA System User Loader User Application Utility ROM Other (RAM) PAGE ADDRESS 0 to ULDR-1 ULDR to UAPP-1 UAPP to top N/A N/A MAXIMUM PRIVILEGE LEVEL High Medium Low High Low
Memory Protection
The optional memory-protection feature separates code memory into three areas: system, user loader, and user application. Code in the system area can be kept confidential. Code in the user areas can be prevented from reading and writing system code. The user loader can also be protected from user application code. Memory protection is implemented using privilege levels for code. Each area has an associated privilege level. RAM/ROM are assigned privilege levels as well. Refer to the MAXQ610 User's Guide for a more thorough explanation of the topic. See Table 1.
Stack Memory
A 16-bit-wide internal stack provides storage for program return addresses and can also be used general-purpose data storage. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and when an interrupt is serviced. An application can also store values in the stack explicitly by using the PUSH, POP, and POPI instructions. On reset, the stack pointer, SP, initializes to the top of the stack (0Fh). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the location pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value at SP and then decrement SP.
The ROM software determines whether the program execution should immediately jump to location 0000h, the start of system code, or to one of the special routines mentioned. Routines within the utility ROM are user accessible and can be called as subroutines by the application software. More information on the utility ROM functions is contained in the MAXQ610 User's Guide. Some applications require protection against unauthorized viewing of program code memory. For these applications, access to in-system programming, inapplication programming, or in-circuit debugging functions is prohibited until a password has been supplied. The password is defined as the 16 words of physical program memory at addresses 0010h to 001Fh. Three password locks are provided for protection of up to three different program memory segments. When the PWL is set to 1 (POR default) and the contents of the memory at addresses 0010h to 001Fh are any value other than FFh or 00h, the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to 0, these utilities are fully accessible without password. The password is automatically set to all ones following a mass erase.
Utility ROM
The utility ROM is a 5.25KB block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines that can be called from application software. These include the following: * In-system programming (bootstrap loader) using JTAG interface * In-circuit debug routines * Test routines (internal memory tests, memory loader, etc.) * User-callable routines for in-application flash programming and fast table lookup Following any reset, execution begins in the utility ROM.
12
Watchdog Timer
An internal watchdog timer greatly increases system reliability. The timer resets the device if software execution is disturbed. The watchdog timer is a free-running counter designed to be periodically reset by the application software. If software is operating correctly, the counter is periodically reset and never reaches its maximum count. However, if software operation is interrupted, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. This protects the system against electrical noise or ESD upsets that could cause uncontrolled processor operation. The internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability.
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16-Bit Microcontroller with Infrared Module
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
WD[1:0] 00 01 10 11 WATCHDOG CLOCK Sysclk/215 Sysclk/218 Sysclk/221 Sysclk/224 WATCHDOG INTERRUPT TIMEOUT 2.7ms 21.9ms 174.7ms 1.4s WATCHDOG RESET AFTER WATCHDOG INTERRUPT (s) 42.7 42.7 42.7 42.7
MAXQ610
The watchdog timer functions as the source of both the watchdog-timer timeout and the watchdog-timer reset. The timeout period can be programmed in a range of 215 to 224 system clock cycles. An interrupt is generated when the timeout period expires if the interrupt is enabled. All watchdog-timer resets follow the programmed interrupt timeouts by 512 system clock cycles. If the watchdog timer is not restarted for another full interval in this time period, a system reset occurs when the reset timeout expires. See Table 2.
can be allowed to continue free-running throughout the receive operation. An overflow occurs when the IR timer value rolls over from 0FFFFh to 0000h. The IR overflow flag (IROV) is set to 1 and an interrupt is generated if enabled (IRIE = 1).
Carrier Generation Module
The IRCAH byte defines the carrier high time in terms of the number of IR input clocks, whereas the IRCAL byte defines the carrier low time. IR Input Clock (fIRCLK) = fSYS/2IRDIV[1:0] Carrier Frequency (fCARRIER) = fIRCLK/(IRCAH + IRCAL + 2) Carrier High Time = IRCAH + 1 Carrier Low Time = IRCAL + 1 Carrier Duty Cycle = (IRCAH + 1)/(IRCAH + IRCAL + 2) During transmission, the IRCA register is latched for each IRV downcount interval and is sampled along with the IRTXPOL and IRDATA bits at the beginning of each new IRV downcount interval so that duty-cycle variation and frequency shifting is possible from one interval to the next, which is illustrated in Figure 1. Figure 2 illustrates the basic carrier generation and its path to the IRTX output pin. The IR transmit polarity bit (IRTXPOL) defines the starting/idle state and the carrier polarity of the IRTX pin when the IR timer is enabled.
IR Carrier Generation and Modulation Timer
The dedicated IR timer/counter module simplifies lowspeed IR communication. The IR timer implements two pins (IRTX and IRRX) for supporting IR transmit and receive, respectively. The IRTX pin has no corresponding port pin designation, so the standard PD, PO, and PI port control status bits are not present. However, the IRTX pin output can be manipulated high or low using the PWCN.IRTXOUT and PWCN.IRTXOE bits when the IR timer is not enabled (i.e., IREN = 0). The IR timer is composed of two separate timing entities: a carrier generator and a carrier modulator. The carrier generation module uses the 16-bit IR Carrier register (IRCA) to define the high and low time of the carrier through the IR carrier high byte (IRCAH) and IR carrier low byte (IRCAL). The carrier modulator uses the IR data bit (IRDATA) and IR Modulator Time register (IRMT) to determine whether the carrier or the idle condition is present on IRTX. The IR timer is enabled when the IR enable bit (IREN) is set to 1. The IR Value register (IRV) defines the beginning value for the carrier modulator. During transmission, the IRV register is initially loaded with the IRMT value and begins down counting towards 0000h, whereas in receive mode it counts upward from the initial IRV register value. During the receive operation, the IRV register can be configured to reload with 0000h when capture occurs on detection of selected edges or
IR Transmission
During IR transmission (IRMODE = 1), the carrier generator creates the appropriate carrier waveform, while the carrier modulator performs the modulation. The carrier modulation can be performed as a function of carrier cycles or IRCLK cycles dependent on the setting of the IRCFME bit. When IRCFME = 0, the IRV downcounter is clocked by the carrier frequency and thus the modulation is a function of carrier cycles. When IRCFME = 1, the IRV downcounter is clocked by IRCLK, allowing carrier modulation timing with IRCLK resolution.
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13
16-Bit Microcontroller with Infrared Module MAXQ610
IRCA IRCA = 0202h IRCA = 0002h
IRMT
IRMT = 3
IRMT = 5 IRCA, IRMT, IRDATA SAMPLED AT END OF IRV DOWNCOUNT INTERVAL 3 2 1 0 5 4 3 2 1 0
CARRIER OUTPUT (IRV)
IRDATA 0 1 0
IR INTERRUPT
IRTX IRTXPOL = 1
IRTX IRTXPOL = 0
Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0)
IRTXPOL CARRIER GENERATION
0 IRTX PIN
IRCLK IRCAH + 1 IRCAL + 1
CARRIER IRCFME 0 1 IRDATA IRMT SAMPLE IRDATA ON IRV = 0000h
1
IR INTERRUPT
CARRIER MODULATION
Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control
14 ______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
The IRTXPOL bit defines the starting/idle state as well as the carrier polarity for the IRTX pin. If IRTXPOL = 1, the IRTX pin is set to a logic-high when the IR timer module is enabled. If IRTXPOL = 0, the IRTX pin is set to a logic-low when the IR timer is enabled. A separate register bit, IR data (IRDATA), is used to determine whether the carrier generator output is output to the IRTX pin for the next IRMT carrier cycles. When IRDATA = 1, the carrier waveform (or inversion of this waveform if IRTXPOL = 1) is output on the IRTX pin during the next IRMT cycles. When IRDATA = 0, the idle condition, as defined by IRTXPOL, is output on the IRTX pin during the next IRMT cycles. The IR timer acts as a downcounter in transmit mode. An IR transmission starts when 1) the IREN bit is set to 1 when IRMODE = 1, 2) the IRMODE bit is set to 1 when IREN = 1, or 3) when IREN and IRMODE are both set to 1 in the same instruction. The IRMT and IRCA registers, along with the IRDATA and IRTXPOL bits, are sampled at the beginning of the transmit process and every time the IR timer value reloads its value. When the IRV reaches 0000h value, on the next carrier clock, it does the following: 1) Reloads IRV with IRMT. 2) Samples IRCA, IRDATA, and IRTXPOL. 3) Generates IRTX accordingly. 4) Sets IRIF to 1. 5) Generates an interrupt to the CPU if enabled (IRIE = 1). To terminate the current transmission, the user can switch to receive mode (IRMODE = 0) or clear IREN to 0. Carrier Modulation Time = IRMT + 1 carrier cycles
MAXQ610
IR Transmit--Independent External Carrier and Modulator Outputs
The normal transmit mode modulates the carrier based upon the IRDATA bit. However, the user has the option to input the modulator (envelope) on an external pin if desired. If the IRENV[1:0] bits are configured to 01b or 10b, the modulator/envelope is output to the IRTXM pin. The IRDATA bit is output directly to the IRTXM pin (if IRTXPOL = 0) on each IRV downcount interval boundary just as if it were being used to internally modulate the carrier frequency. If IRTXPOL = 1, the inverse of the IRDATA bit is output to the IRTXM pin on the IRV interval downcount boundaries. The envelope output is illustrated in Figure 4. When the envelope mode is enabled, it is possible to output either the modulated (IRENV[1:0] = 01b) or unmodulated (IRENV[1:0] = 10b) carrier to the IRTX pin.
IRMT = 3
CARRIER OUTPUT (IRV)
3
2
1
0
3
2
1
0
IRDATA 0 1 0
IR INTERRUPT
IRTX IRTXPOL = 1
IRTX IRTXPOL = 0
Figure 3. IR Transmission Waveform (IRCFME = 0)
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16-Bit Microcontroller with Infrared Module MAXQ610
IRTXM IRTXPOL = 1 IRTXM IRTXPOL = 0
IRDATA 1 0 1 0 1 0 1 0
IR INTERRUPT IRV INTERVAL IRMT IRMT IRMT IRMT
Figure 4. External IRTXM (Modulator) Output
CARRIER GENERATION
IRCLK 0 IRCAH + 1 IRCAL + 1 1 IRCFME
CARRIER MODULATION IR TIMER OVERFLOW INTERRUPT TO CPU 0000h IRV IR INTERRUPT COPY IRV TO IRMT ON EDGE DETECT IRXRL
IRRX PIN
RESET IRV TO 0000h EDGE DETECT IRDATA
Figure 5. IR Capture
IR Receive
When configured in receive mode (IRMODE = 0), the IR hardware supports the IRRX capture function. The IRRXSEL[1:0] bits define which edge(s) of the IRRX pin should trigger IR timer capture function. The IR module starts operating in the receive mode when IRMODE = 0 and IREN = 1. Once started, the IR timer (IRV) starts up counting from 0000h when a quali-
fied capture event as defined by IRRXSEL happens. The IRV register is, by default, counting carrier cycles as defined by the IRCA register. However, the IR carrier frequency detect (IRCFME) bit can be set to 1 to allow clocking of the IRV register directly with the IRCLK for finer resolution. When IRCFME = 0, the IRCA defined carrier is counted by IRV. When IRCFME = 1, the IRCLK clocks the IRV register.
16
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16-Bit Microcontroller with Infrared Module
On the next qualified event, the IR module does the following: 1) Captures the IRRX pin state and transfers its value to IRDATA. If a falling edge occurs, IRDATA = 0. If a rising edge occurs, IRDATA = 1. 2) Transfers its current IRV value to the IRMT. 3) Resets IRV content to 0000h (if IRXRL = 1). 4) Continues counting again until the next qualified event. If the IR timer value rolls over from 0FFFFh to 0000h before a qualified event happens, the IR timer overflow (IROV) flag is set to 1 and an interrupt generated if enabled. The IR module continues to operate in receive mode until it is stopped by switching into transmit mode (IRMODE = 1) or clearing IREN = 0.
MAXQ610
Carrier Burst-Count Mode
A special mode reduces the CPU processing burden when performing IR learning functions. Typically, when operating in an IR learning capacity, some number of carrier cycles are examined for frequency determination. Once the frequency has been determined, the IR receive function can be reduced to counting the number of carrier pulses in the burst and the duration of the combined mark-space time within the burst. To simplify this process, the receive burst-count mode (as enabled by the RXBCNT bit) can be used. When RXBCNT = 0, the standard IR receive capture functionality is in place.
CARRIER FREQUENCY CALCULATION
IRMT = PULSE COUNTING IRV = CARRIER CYCLE COUNTING
IRMT = PULSE COUNTING
IRRX
IRV IRMT
1
2
3
4 5
6
7
8 9
1 TO 4
CAPTURE INTERRUPT (IRIF = 1). IRV IRMT. IRV = 0 (IF IRXRL = 1). SOFTWARE SETS IRCA = CARRIER FREQUENCY. SOFTWARE SETS RXBCNT = 1 (WHICH CLEARS IRMT = 0001 IN HARDWARE). SOFTWARE CLEARS IRCFME = 0 SO THAT IRV COUNTS CARRIER CYCLES. IRV IS RESET TO 0 ON QUALIFIED EDGE DETECTION IF IRXRL = 1. SOFTWARE ADDS TO IRMT THE NUMBER OF PULSES USED FOR CARRIER MEASUREMENT. IRCA x 2x COUNTER FOR SPACE CAN BEGIN IMMEDIATELY (QUALIFIED EDGE RESETS). QUALIFIED EDGE DETECTED: IRMT++ IRV RESET TO 0 IF IRXRL = 1. IRCA x 2 PERIOD ELAPSES: IRIF = 1; CARRIER ABSENCE = SPACE. BURST MARK = IRMT PULSES. SOFTWARE CLEARS RXBCNT = 0 SO THAT WE CAPTURE ON THE NEXT QUALIFIED EDGE. QUALIFIED EDGE DETECTED: IRIF = 1, CAPTURE IRV IRMT AS THE BURST SPACE (PLUS UP TO ONE CARRIER CYCLE). SOFTWARE SET RXBCNT = 1 AS IN (5). CONTINUE (5) TO (8) UNTIL LEARNING SPACE EXCEEDS SOME DURATION. IRV ROLLOVERS CAN BE USED.
5
6
7
8 9
Figure 6. Receive Burst-Count Example
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16-Bit Microcontroller with Infrared Module
When RXBCNT = 1, the IRV capture operation is disabled and the interrupt flag associated with the capture no longer denotes a capture. In the carrier burst-count mode, the IRMT register is now used only to count qualified edges. The IRIF interrupt flag (normally used to signal a capture when RXBCNT = 0) now becomes set if ever two IRCA cycles elapse without getting a qualified edge. The IRIF interrupt flag thus denotes absence of the carrier and the beginning of a space in the receive signal. When the RXBCNT bit is changed from 0 to 1, the IRMT register is set to 0001h. The IRCFME bit is still used to define whether the IRV register is counting system IRCLK clocks or IRCA-defined carrier cycles. The IRXRL bit is still used to define whether the IRV register is reloaded with 0000h on detection of a qualified edge (per the IRXSEL[1:0] bits). Figure 6 and the descriptive sequence embedded in the figure illustrate the expected usage of the receive burst-count mode. While the microcontroller is in a reset state, all port pins become high impedance with weak pullups disabled, unless otherwise noted. From a software perspective, each port appears as a group of peripheral registers with unique addresses. Special function pins can also be used as general-purpose I/O pins when the special functions are disabled. For a detailed description of the special functions available for each pin, refer to the part-specific user manual. The MAXQ610 User's Guide describes all special functions available on the MAXQ610.
MAXQ610
USART
The USART units are implemented with the following characteristics: * 2-wire interface * Full-duplex operation for asynchronous data transfers * Half-duplex operation for synchronous data transfers * Programmable interrupt for receive and transmit * Independent baud-rate generator * Programmable 9th bit parity support * Start/stop bit support
16-Bit Timers/Counters
The MAXQ610 provides two timers/counters that support the following functions: * 16-bit timer/counter * 16-bit up/down autoreload * Counter function of external pulse * 16-bit timer with capture * 16-bit timer with compare * Input/output enhancements for pulse-width modulation * Set/reset/toggle output state on comparator match * Prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10)
Serial Peripheral Interface (SPI)
The integrated SPI provides an independent serial communication channel that communicates synchronously with peripheral devices in a multiple master or multiple slave system. The interface allows access to a 4-wire, full-duplex serial bus, and can be operated in either master mode or slave mode. Collision detection is provided when two or more masters attempt a data transfer at the same time. The maximum SPI master transfer rate is Sysclk/2. When operating as an SPI slave, the MAXQ610 can support up to a Sysclk/4 SPI transfer rate. Data is transferred as an 8-bit or 16-bit value, MSB first. In addition, the SPI module supports configuration of active SSEL state through the slave active select.
General-Purpose I/O
The MAXQ610 provides port pins for general-purpose I/Os that have the following features: * CMOS output drivers * Schmitt trigger inputs * Optional weak pullup to VDD when operating in input mode
Table 3. USART Mode Details
MODE Mode 0 Mode 1 Mode 2 Mode 3 TYPE Synchronous Asynchronous Asynchronous Asynchronous START BITS N/A 1 1 1 DATA BITS 8 8 8+1 8+1 STOP BITS N/A 1 1 1
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16-Bit Microcontroller with Infrared Module MAXQ610
SHIFT SSEL SAMPLE SHIFT SAMPLE
tMCK SCLK CKPOL/CKPHA 0/1 OR 1/0 tMCH SCLK CKPOL/CKPHA 0/0 OR 1/1 tMOH tMOV MOSI MSB MSB-1 tRF LSB tMLH tMCL
tMIS MISO MSB MSB-1
tMIH LSB
Figure 7. SPI Master Communication Timing
SHIFT SSEL
SAMPLE
SHIFT
SAMPLE tSSH tSD
tSSE tSCK
SCLK CKPOL/CKPHA 0/1 OR 1/0 tSCH SCLK CKPOL/CKPHA 0/0 OR 1/1 tSCL
tSIS MOSI MSB MSB-1
tSIH LSB
tSOV MISO MSB MSB-1
tRF LSB
tSLH
Figure 8. SPI Slave Communication Timing
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16-Bit Microcontroller with Infrared Module MAXQ610
On-Chip Oscillator
An external quartz crystal or a ceramic resonator can be connected between HFXIN and HFXOUT on the MAXQ610, as illustrated in Figure 9. Noise at HFXIN and HFXOUT can adversely affect onchip clock timing. It is good design practice to place the crystal and capacitors near the oscillator circuitry and connect HFXIN and HFXOUT to ground with a direct short trace. The typical values of external capacitors vary with the type of crystal to be used and should be initially selected based on the load capacitance as suggested by the crystal manufacturer. ty is not required, a commercial gang programmer can be used for mass programming. Activating the JTAG interface and loading the test access port (TAP) with the system programming instruction invokes the bootstrap loader. Setting the SPE bit to 1 during reset through the JTAG interface executes the bootstraploader-mode program that resides in the utility ROM. When programming is complete, the bootstrap loader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software. In addition, the ROM loader also enforces the memoryprotection policies. 16-word passwords are required to access the ROM loader interface. Loading memory is not possible for ROM-only versions of the MAXQ610 family.
ROM Loader
The MAXQ610 includes a ROM loader. The loader denies access to the system, user loader, or user-application memories unless an area-specific password is provided. The ROM loader is not available in ROM-only versions of the MAXQ610.
In-Application Flash Programming
From user-application code, flash can be programmed using the ROM utility functions from either C or assembly language. The function declarations that follow show examples of some of the ROM utility functions provided for in-application flash programming. /* Write one 16-bit word to code address 'dest'. * Dest must be aligned to 16 bits. * Returns 0 = failure, 1 = OK. */ int flash_write (uint16_t dest, uint16_t data);
Loading Flash Memory
An internal bootstrap loader allows the device to be reloaded over a simple JTAG interface. As a result, software can be upgraded in-system, eliminating the need for a costly hardware retrofit when updates are required. Remote software uploads are possible that enable physically inaccessible applications to be frequently updated. The interface hardware can be a JTAG connection to another microcontroller, or a connection to a PC serial port using a serial-to-JTAG converter, such as the MAXQJTAG-001 available from Maxim Integrated Products. If in-system programmabili-
VDD HFXIN STOP RF C1 HFXOUT C2 RF = 1M 50% C1 = C2 = 30pF MAXQ610
CLOCK CIRCUIT
Figure 9. On-Chip Oscillator
20
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16-Bit Microcontroller with Infrared Module
To erase, the following function would be used: /* Erase the given Flash page * addr: Flash offset (anywhere within page) */ int flash_erasepage(uint16_t addr); The in-application flash programming must call ROM utility functions to erase and program any of the flash memory. Memory protection is enforced by the ROM utilty functions. In-application programming is not available in ROMonly versions of the MAXQ610 family. 1) Background Mode * CPU is executing the normal user program. * Allows the host to configure and set up the in-circuit debugger. 2) Debug Mode * The debugger takes over the control of the CPU. * Read/write accesses to internal registers and memory. * Single-step of the CPU for trace operation. The interface to the debug engine is the TAP controller. The interface allows for communication with a bus master that can either be automatic test equipment or a component that interfaces to a higher level test bus as part of a complete system. The communication operates across a 4-wire serial interface from a dedicated TAP that is compatible to the JTAG IEEE Std 1149. The TAP provides an independent serial channel to communicate synchronously with the host system. To prevent unauthorized access of the protected memory regions through the JTAG interface, the debug engine prevents modification of the privilege registers and disallows all access to system memory, unless memory protection is disabled. In addition, all services (such as register display or modification) are denied when code is executing inside the system area. The debugger is not available for ROM-only versions of the MAXQ610 family.
MAXQ610
In-Circuit Debug and JTAG Interface
Embedded debug hardware and software are developed and integrated into the MAXQ610 to provide full in-circuit debugging capability in a user application environment. These hardware and software features include: * A debug engine. * A set of registers providing the ability to set breakpoints on register, code, or data using debug service routines stored in ROM. Collectively, these hardware and software features support two modes of in-circuit debug functionality:
MAXQ610
DEBUG SERVICE ROUTINES (UTILITY ROM)
CPU DEBUG ENGINE TMS TCK TDI TDO TAP CONTROLLER CONTROL BREAKPOINT ADDRESS DATA
Figure 10. In-Circuit Debugger
______________________________________________________________________________________
21
16-Bit Microcontroller with Infrared Module MAXQ610
Operating Modes
The lowest power mode of operation for the MAXQ610 is stop mode. In this mode, CPU state and memories are preserved, but the CPU is not actively running. Wake-up sources include external I/O interrupts, the power-fail warning interrupt, or a power-fail reset. Any time the microcontroller is in a state where code does not need to be executed, the user software can put the MAXQ610 into stop mode. The nanopower ring oscillator is an internal ultra-low-power (400nA), 8kHz ring oscillator that can be used to drive a wake-up timer that exits stop mode. The wake-up timer is programmable by software in steps of 125s up to approximately 8s. The power-fail monitor is always on during normal operation. However, it can be selectively disabled during stop mode to minimize power consumption. This feature is enabled using the power-fail monitor disable (PFD) bit in the PWCN register. The reset default state for the PFD bit is 1, which disables the power-fail monitor function during stop mode. If power-fail monitoring is disabled (PFD = 1) during stop mode, the circuitry responsible for generating a power-fail warning or reset is shut down and neither condition is detected. Thus, the VDD < VRST condition does not invoke a reset state. However, in the event that VDD falls below the POR level, a POR is generated. The power-fail monitor is enabled prior to stop mode exit and before code execution begins. If a power-fail warning condition (VDD < VPFW) is then detected, the power-fail interrupt flag is set on stop mode exit. If a power-fail condition is detected (VDD < VRST), the CPU goes into reset.
Power-Fail Detection
Figures 11, 12, and 13 show the power-fail detection and response during normal and stop mode operation.
VDD
t < tPFW C
t tPFW
t tPFW
t tPFW
VPFW G VRST E F B D H
VPOR I A
INTERNAL RESET (ACTIVE HIGH)
Figure 11. Power-Fail Detection During Normal Operation
22
______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
Table 4. Power-Fail Detection States During Normal Operation
STATE A B POWER-FAIL On On INTERNAL REGULATOR Off On CRYSTAL OSCILLATOR Off On SRAM RETENTION -- -- VDD < V POR. VPOR < VDD < VRST. Crystal warmup time, t XTAL_RDY. CPU held in reset. VDD > VRST. CPU normal operation. Power drop too short. Power-fail not detected. VRST < VDD < V PFW. PFI is set when VRST < VDD < VPFW and maintains this state for at least t PFW, at which time a powerfail interrupt is generated (if enabled). CPU continues normal operation. VPOR < VDD < VRST. Power-fail detected. CPU goes into reset. Power-fail monitor turns on periodically. VDD > VRST. Crystal warmup time, t XTAL_RDY. CPU resumes normal operation from 8000h. VPOR < VDD < VRST. Power-fail detected. CPU goes into reset. Power-fail monitor is turned on periodically. VDD < V POR. Device held in reset. No operation allowed. COMMENTS
MAXQ610
C D
On On
On On
On On
-- --
E
On
On
On
--
F
On (Periodically)
Off
Off
Yes
G
On
On
On
--
H
On (Periodically)
Off
Off
Yes
I
Off
Off
Off
--
If a reset is caused by a power-fail, the power-fail monitor can be set to one of the following intervals: * Always on--continuous monitoring * 211 nanopower ring oscillator clocks (~256ms) * 212 nanopower ring oscillator clocks (~512ms) * 213 nanopower ring oscillator clocks (~1.024s) In the case where the power-fail circuitry is periodically turned on, the power-fail detection is turned on for two nanopower ring oscillator cycles. If VDD > VRST during
detection, VDD is monitored for an additional nanopower ring oscillator period. If VDD remains above VRST for the third nanopower ring period, the CPU exits the reset state and resumes normal operation from utility ROM at 8000h after satisfying the crystal warmup period. If a reset is generated by any other event, such as the RESET pin being driven low externally or the watchdog timer, the power-fail, internal regulator, and crystal remain on during the CPU reset. In these cases, the CPU exits the reset state in less than 20 crystal cycles after the reset source is removed.
______________________________________________________________________________________
23
16-Bit Microcontroller with Infrared Module MAXQ610
VDD A t < tPFW t tPFW t tPFW
VPFW D VRST B C E VPOR F
STOP
INTERNAL RESET (ACTIVE HIGH)
Figure 12. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
STATE POWER-FAIL INTERNAL REGULATOR Off CRYSTAL OSCILLATOR Off SRAM RETENTION Yes COMMENTS Application enters stop mode. VDD > VRST. CPU in stop mode. Power drop too short. Power-fail not detected. VRST < VDD < V PFW. Power-fail warning detected. Turn on regulator and crystal. Crystal warmup time, t XTAL_RDY. Exit stop mode. Application enters stop mode. VDD > VRST. CPU in stop mode. VPOR < VDD < VRST. Power-fail detected. CPU goes into reset. Power-fail monitor is turned on periodically. VDD < V POR. Device held in reset. No operation allowed.
A
On
B
On
Off
Off
Yes
C
On
On
On
Yes
D
On
Off
Off
Yes
E
On (Periodically)
Off
Off
Yes
F
Off
Off
Off
--
24
______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module MAXQ610
VDD A D VPFW VRST B C
E VPOR F
STOP
INTERNAL RESET (ACTIVE HIGH)
INTERRUPT
Figure 13. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
STATE POWER-FAIL INTERNAL REGULATOR Off CRYSTAL OSCILLATOR Off SRAM RETENTION Yes COMMENTS Application enters stop mode. VDD > VRST. CPU in stop mode. VDD < V PFW. Power-fail not detected because power-fail monitor is disabled. VRST < VDD < V PFW. An interrupt occurs that causes the CPU to exit stop mode. Power-fail monitor is turned on, detects a powerfail warning, and sets the power-fail interrupt flag. Turn on regulator and crystal. Crystal warmup time, t XTAL_RDY. On stop mode exit, CPU vectors to the higher priority of power-fail and the interrupt that causes stop mode exit.
A
Off
B
Off
Off
Off
Yes
C
On
On
On
Yes
______________________________________________________________________________________
25
16-Bit Microcontroller with Infrared Module MAXQ610
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled (continued)
STATE POWER-FAIL INTERNAL REGULATOR Off CRYSTAL OSCILLATOR Off SRAM RETENTION Yes COMMENTS Application enters stop mode. VDD > VRST. CPU in stop mode. VPOR < VDD < VRST. An interrupt occurs that causes the CPU to exit stop mode. Power-fail monitor is turned on, detects a powerfail, puts CPU in reset. Power-fail monitor is turned on periodically. VDD < V POR Device held in reset. No operation allowed.
D
Off
E
On (Periodically)
Off
Off
Yes
F
Off
Off
Off
--
Applications Information
The low-power, high-performance RISC architecture of this device makes it an excellent fit for many portable or battery-powered applications. It is ideally suited for applications such as universal remote controls that require the cost-effective integration of IR transmit/ receive capability.
Differences for ROM Versions
The ROM-only versions of the MAXQ610 family devices operate in the same manner as their flash counterparts with the following exceptions: * The ROM loader is not available in the ROM version. * Loading memory and in-application programming are not supported. * The debugger is not available in the ROM version.
Grounds and Bypassing
Careful PCB layout significantly minimizes system-level digital noise that could interact with the microcontroller or peripheral components. The area under any digital components should be a continuous ground plane if possible. Keep any bypass capacitor leads short for best noise rejection and place the capacitors as close to the leads of the devices as possible. CMOS design guidelines for any semiconductor require that no pin be taken above V DD or below GND. Violation of this guideline can result in a hard failure (damage to the silicon inside the device) or a soft failure (unintentional modification of memory contents). Voltage spikes above or below the device's absolute maximum ratings can potentially cause a devastating IC latchup. Microcontrollers commonly experience negative voltage spikes through either their power pins or generalpurpose I/O pins. Negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. Devices such as keypads can conduct electrostatic discharges directly into the microcontroller and seriously damage the device. System designers must protect components against these transients that can corrupt system memory.
Additional Documentation
Designers must have the following documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user's guides offer detailed information about device features and operation. The following documents can be downloaded from www.maxim-ic.com/microcontrollers. * This MAXQ610 data sheet, which contains electrical/ timing specifications and pin descriptions. * The MAXQ610 revision-specific errata sheet (www.maxim-ic.com/errata). * The MAXQ610 User's Guide, which contains detailed information on core features and operation, including programming.
26
______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
Development and Technical Support
Maxim and third-party suppliers provide a variety of highly versatile, affordably priced development tools for this microcontroller, including the following: * Compilers * In-circuit emulators * Integrated Development Environments (IDEs) * JTAG-to-serial converters for programming and debugging A partial list of development tool vendors can be found at www.maxim-ic.com/MAXQ_tools. Technical support is available at https://support.maximic.com/micro.
MAXQ610
Selector Guide
PART MAXQ610A-0000+ MAXQ610B-0000+ MAXQ610J-0000+ MAXQ610X-0000+ OPERATING VOLTAGE (V) 1.70 to 3.6 1.70 to 3.6 1.70 to 3.6 1.70 to 3.6 PROGRAM MEMORY (KB) 64 Flash 64 Flash 64 Flash 64 Flash DATA MEMORY (KB) 2 2 2 2 PIN-PACKAGE 32 TQFN-EP 40 TQFN-EP 44 TQFN-EP Bare die
Note: Contact factory for information about masked ROM devices.
Pin Configurations
P3.5/INT13 P3.4/INT12 P2.2/SCLK P2.1/MISO P2.0/MOSI P2.3/SSEL P1.5/INT5 P1.7/INT7 P1.7/INT7 P1.6/INT6 P2.4/TCK P1.6/INT6 HXFOUT HFXOUT
GND
N.C.
TOP VIEW
HFXIN
TOP VIEW
24 P2.5/TDI 25 P2.6/TMS 26 P2.7/TDO 27 RESET 28 VDD 29 GND 30 IRTX 31 IRRX 32 1 P0.0/IRTXM
23
22
21
20
19
18
17 16 15 14 13 P1.4/INT4 VDD REGOUT GND P1.3/INT3 P1.2/INT2 P1.1/INT1 P1.0/INT0 P2.4/TCK 31 P2.5/TDI 32 P3.6/INT14 33 P3.7/INT15 34 P2.6/TMS 35 P2.7/TDO 36 RESET 37 VDD 38 IRTX 39 IRRX 40
30 29 28 27 26 25 24 23 22 21 20 P1.5/INT5 19 P1.4/INT4 18 VDD 17 REGOUT 16 P3.3/INT11 MAXQ610 15 P3.2/INT10 14 P1.3/INT3
MAXQ610
12 11
+
2 P0.1/RX0 3 P0.2/TX0 4 P0.3/RX1 5 P0.4/TX1 6 P0.5/TBA0/TBA1
*EP
10 9
HFXIN 13 P1.2/INT2 12 P1.1/INT1 11 P1.0/INT0 10 P0.7/TBB1
+
*EP
7 P0.6/TBB0
8 P0.7/TBB1
1 P0.0/IRTXM
2 P3.0/INT8
3 P0.1/RX0
4 P3.1/INT9
5 P0.2/TX0
6 P0.3/RX1
7 P0.4/TX1
8 P0.5/TBA0/TBA1
9 P0.6/TBB0
THIN QFN (5mm x 5mm)
*EXPOSED PAD = GND. *EXPOSED PAD = GND.
THIN QFN (6mm x 6mm)
______________________________________________________________________________________
27
16-Bit Microcontroller with Infrared Module MAXQ610
Pin Configurations (continued)
P2.2.SCLK P3.5/INT13 P3.4/INT12 P2.0/MOSI P2.1/MISO P2.3/SSEL P1.7/INT7 P1.6/INT6
25
33
32
31
30
29
28
27
26
24
P2.4/TCK P2.5/TDI P3.6/INT14 P3.7/INT15 P2.6/TMS P2.7/TDO RESET VDD GND IRTX IRRX
23
HFXIN
TOP VIEW
HFXOUT
GND
34 35 36 37 38 39 40 41 42 43 44 10 11 1 2 3 4 5 6 7 8 9
22 21 20 19 18 17 16 15 14
P1.5/INT5 P1.4/INT4 GND VDD REGOUT GND P3.3/INT11 P3.2/INT10 P1.3/INT3 P1.2/INT2 P1.1/INT1
MAXQ610
+
*EP
13 12
P0.5/TBA0/TBA1
P0.0/IRTXM
P3.0/INT8 P0.1/RX0
P0.2/TX0
P0.3/RX1
P0.4/TX1
P0.6/TBB0
P0.7/TBB1
R3.1/INT9
TQFN
*EXPOSED PAD = GND.
P1.0/INT0
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 32 TQFN-EP 40 TQFN-EP 44 TQFN-EP PACKAGE CODE T3255+3 T4066+2 T4477+2 DOCUMENT NO. 21-0140 21-0141 21-0144
28
______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
Revision History
REVISION NUMBER 0 REVISION DATE 10/08 Initial release. Removed the Sysclk = 1MHz condition for the Active Current parameter, changed the RPU min values from 18k and 19k to 16k and 17k , and changed the fNANO TA = +25C min and max values from 4.2kHz and 14.0kHz to 3.0kHz and 20.0kHz, respectively, in the Recommended DC Operating Conditions table. Added the sentence "Software must configure this pin after release from reset to remove the high-impedance input condition." to the IRRX, P0.x, P1.x, P2.x, and P3.x descriptions in the Pin Description table. Added future status to the 32 TQFN package in the Ordering Information table. 2 1/09 In the Pin Description table, changed the REGOUT pin series resistance from 1 2 to 10 . to DESCRIPTION PAGES CHANGED --
MAXQ610
4, 5
1
11/08
8, 9 1 8 5 25
3
7/09
Changed the t IRRX_A minimum spec from 200ns to 300ns in the Recommended DC Operating Conditions table. Removed the statement about the use of multilayer boards from the Grounds and Bypassing section.
4
10/09
Adjusted the minimum resonator frequency from DCMHz to 1MHz and the minimum programming frequency from 5MHz to 6MHz in the Recommended DC Operating Conditions table. Added the 44-pin TQFN package.
5, 6 1, 8, 9, 10, 26, 27, 28
5
2/10
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29
(c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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